1. Field of Disclosure
The present disclosure of invention relates to a flexible substrate having a via-hole and a method for manufacturing the flexible substrate, and more specifically the present disclosure of invention relates to a flexible substrate having a vertical via-hole with a conductive material for an electric connecting and having relatively low dielectric constant.
2. Description of Related Technology
Recently, a plurality of semiconductor chips is vertically stacked in addition to manufacturing a fine circuit in manufacturing a semiconductor, to complete or perform a complex circuit in the semiconductor.
Here, a method in which various kinds of semiconductor chips or wafers are vertically stacked and are connected with each other through a via-hole may be called as system in package (SiP).
In the SiP, a plurality of chips is vertically stacked to minimize a size of the semiconductor. Thus, forming the via-hole for connecting may be a core technology in the SiP.
In addition, in a recent developed semiconductor device, a flexible device is more necessary. Here, in the flexible device, compared to a conventional silicon based semiconductor device, manufacturing processes are formed on a polymer substrate such as polyimide, polyethylene phthalate (PET), polydimethylsiloxane (PDMS), ecoflex and so on, or a polished silicon based device with a relatively small thickness is mounted on the polymer substrate.
To electrically connect the silicon based devices with each other, thorough silicon via (TSV) is spotlighted recently. In the TSV, a plurality of substrates is stacked and a via-hole passing through the substrates vertically is formed to connect the substrates electrically.
In the conventional TSV, a step of via formation, a step of via filling, and a step of planarization are included. In the via formation, a vertical via-hole having a high aspect ratio is formed using a deep reactive ion etching. In the via filling, the via-hole is filled via an electroplating after forming a dielectric layer, a diffusion barrier layer and a seed layer. In the planarization, the via-hole is planarized via a chemical mechanical polishing (CMP).
In forming the vertical via-hole through the flexible substrate, the dielectric layer and the diffusion barrier layer are unnecessary to be formed, and thus a process may be simplified. However, in using the deep reactive ion etching, the via-hole having the high aspect ratio may be hard to be formed, and a heat generated in forming a plasma may damage the flexible substrate.
In addition, in the electroplating, a void may be formed and thus electric characteristics may be decreased.
As for a prior art, Korean laid-open patent application No. 10-2005-0122630 discloses an electroplating forming a relatively thick metal layer.